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General Information
    • ISSN: 2010-3689
    • Frequency: Bimonthly (2011-2014); Monthly (Since 2015)
    • DOI: 10.18178/IJIET
    • Editor-in-Chief: Prof. Dr. Steve Thatcher
    • Executive Editor: Ms. Nancy Y. Liu
    • Abstracting/ Indexing: EI (INSPEC, IET), Electronic Journals Library, Google Scholar, Crossref and ProQuest
    • E-mail: ijiet@ejournal.net
Editor-in-chief
Prof. Dr. Steve Thatcher
University of South Australia, Australia
It is my honor to be the editor-in-chief of IJIET. The journal publishes good papers which focous on the advanced researches in the field of information and education technology. Hopefully, IJIET will become a recognized journal among the scholars in the filed of information and education technology.
IJIET 2011 Vol.1(1): 68-73 ISSN: 2010-3689
DOI: 10.7763/IJIET.2011.V1.12

Table Memory and Controller Implementation Scheme in FPGA for Hard Real Time Control Systems

Gillani Ghayoor Abbas, Yian Zhu, Amjad Hafiz Muhammad, Ahmad Waqar and Jianfeng An

Abstract—High level of reliability is needed by the backplane bus for the Aircraft Information Management System (AIMS) that can ensure the robust and fault tolerant communication between its Line Replaceable Modules (LRM), which in turns ensures the safety critical hard real time control system operation. As the time driven protocol is more reliable than the event driven protocols, this backplane bus needs to be implemented with time division control protocol. For that matter, more attention is needed to ensure the synchronization issues between LRMs. This paper is the extension of our previous work and addresses Table memory and Controller implementation scheme for the Bus Interface Onit (BIU). The aforesaid system is developed for ARINC 659 backplane bus as an example, which controls all the BIU operations. The table memory introduces the cabin wide harmony by providing the same command sequence for all the LRMs. This command sequence also includes the source and destination addresses that avoids extra load on the backplane bus. The controller needs to fetch the commands from the table memory, decode them and then execute them to drive the bus for the BIU operations including message operations and synchronization handling. We have designed the Instruction Set Architecture (ISA) for table commands and implemented three Finite State Machines (FSM) for designing this controller along with some glue logic. First FSM is meant for managing commands, second for managing the BIU current state for synchronization needs, and the third for controlling the BIU operations. The aforesaid design has been modeled by using Verilog, Hardware Descriptive Language (HDL) and implemented in Altera Cyclone II board. Results of Modelsim and Quartus proved the cycle accurate implementation of controller in compliance with ARINC 659 specifications.

Index TermsBackplane bus controller;Table Memory; FPGA; Hard Real Time control system; ARINC 659; AIMS

School of Computer Science and Technology Northwestern, Polytechnical University,710072, Xi’an, China (email: itsghayoor@yahoo.com)

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Cite: Gillani Ghayoor Abbas, Yian Zhu, Amjad Hafiz Muhammad, Ahmad Waqar and Jianfeng An, "Table Memory and Controller Implementation Scheme in FPGA for Hard Real Time Control Systems," International Journal of Information and Education Technology vol. 1, no. 1, pp. 68-73, 2011.

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